A flash ADC comprises a set of comparators, each with a different threshold. For ADC comparators, the thresholds are normally linearly spaced with respect to each other, although this constraint is not necessary. An important constraint is that the thresholds be known to the downstream digital signal processor (DSP). For a bank of comparators arranged such that they are evenly and linearly spaced, such that the threshold voltage between any two thresholds is the same, the quality of the data conversion depends on the linearity of that spacing. An example implementation with 16 threshold levels would provide a data convertor of 4 bits (since 24=16). This would require 16 evenly spaced thresholds. If the thresholds are not evenly spaced, the effective resolution of ADC is lower than 16.
Often, the comparator set is preceded by a single sample and hold circuit, which samples the input signal and holds its output while the comparators make the comparison to their respective thresholds.
The “hold” cycle of a sample and hold circuit is imperfect in the sense that the output signal may still be changing at the input to the comparators, particularly for very high speed flash ADCs. Other flash ADCs forego the sample and hold, which virtually guarantees that the signal will be changing while the comparators are making their decision.
The comparators in an ADC are normally clocked; such comparators are also referred to herein as “samplers”. Ideally each sampler samples the input signal at the same instant. The samplers are analog circuits whose ideal input-output relationship can be described as:outputk(iT)=sign(input(iT)−thresholdk)  Equation 1where i is the sample index (the ith sample), and T is the sampling period and k is the kth comparator in a set of comparators.
However the real-life, or non-ideal, behavior of the sampler and sample and hold circuit introduces a threshold offset, and a sampling time offset, thereby distorting the kth sampler as shown below.outputk(iT)=sign(input(iT+apertureErrork)−thresholdk+offsetk)  Equation 2where apertureErrork is the timing error of the kth sampler. The aperture timing error can in general be different for each sampler. In the present disclosure, the “common mode” aperture error is the average of all the individual aperture errors, and the “differential mode” aperture error is the difference between any two aperture sampling times.
It is desirable to remove the effect of apertureErrork and offsetk with calibration. The present disclosure addresses apertureErrork.
There are two categories of calibration: foreground and background. Foreground calibration refers to a procedure performed in such a way as to disrupt the normal signal flow through the ADC, often by temporarily removing the normal ADC input signal and introducing a known calibration input signal. By doing so, during foreground calibration the system in which the ADC is performing the data conversion is not able to process the normal input signal. This disruption can sometimes be tolerated at certain times in the life cycle of the system with the ADC, perhaps for a brief time at power up.
Background calibration refers to a calibration procedure in which the normal signal flow of the system with the ADC is not disrupted in any way; the system can continue to process data from the ADC and expect the conversion performance to be within specified bounds, and expect that the normal input signal is being converted.
In an implementation, a flash ADC is a single set of comparators which all sample the input signal at the same instant. Such an ADC implementation is shown in FIG. 1A. Very high speed flash ADCs often employ “time-interleaving” in which a total flash ADC comprises several time-interleaved sub-ADCs, as shown in FIG. 1B which illustrates a two-phase interleaved flash. In an example using time-interleaved sub-ADCs, as shown in FIG. 1B, each sub-ADC comprises a set of comparators running off a different phase of a lower speed clock. Time-interleaving allows samplers to run off of a slower clock while maintaining the higher speed net sampling frequency.
Recall the input-output relationship of an analog sampler:outputk(iT)=sign(input(iT+apertureErrork)−thresholdk+offsetk)  Equation 3
Estimating and calibrating the offsetk is the subject of the related commonly assigned U.S. patent application Ser. No. 13/766,855 (Attorney Ref. PAT 7079-2) entitled “Background Calibration of Threshold Errors in Analog to Digital Converters”.
It is desirable to estimate and reduce apertureErrork.
FIG. 2 illustrates a grid 10 as a representation of a time-interleaved flash ADC, in which time is on the horizontal axis and threshold amplitude is on the vertical axis. Ideally, voltage is spaced linearly or vertically, as shown by the ideal times and amplitudes 12 in FIG. 2. However, since it is also desirable to have the comparators spaced linearly in time (to achieve time-interleaving), which is shown horizontally, the threshold voltage would be interleaved. The horizontal spacing stands for when the sample occurs, which is also shown in FIG. 2.
FIG. 3 illustrates the impact of threshold errors due to sampler offsets. The measured values 14 include threshold errors, and move up and down with respect to the ideal values 12; the measured values 14 are not evenly spaced, and require correction.
FIG. 4 illustrates the impact of both threshold and aperture timing errors by illustrating measured values 16 which include threshold and aperture center errors. The aperture timing errors are represented in the values 16 by a shift to the left and right with respect to the ideal. For a given column of samplers, it is desirable that all samplers sample at the same time. Because the input signal could be changing, if samples are taken too early or too late with respect to the ideal value, this can result in not properly representing the analog signal at a given time, which is undesirable.
As shown in FIG. 5, a problem arises when an analog signal 18 passes between the measured timing instants, or measured values, 16 of two samplers. FIG. 5 illustrates that there could be a problem if the samples are not sampling at the same instant, which is illustrated as lined up horizontally. If the analog signal happens to slip in between two of the measured values 16 as shown, this results in an error as shown in FIG. 6.
FIG. 6 illustrates the output of the individual samplers in the scenario of FIG. 5, showing occurrence of a “sparkle code” or “bubble”, which is defined as a 0 between two 1s. In FIG. 6, ideal values 20 are the output of the ideal sampler, while measured values 22 are the measured output of a real sampler, including amplitude and aperture timing errors. The sampler output should be a 1 if the analog signal is above the threshold, and the output should be 0 if the analog signal is below the threshold.
In FIG. 6, the ideal sampler output values at samplers 24 and 26 are 1. The ideal output value at sampler 28 is 0, since the analog signal 18 is below the ideal threshold 12. This indicates that, based on ideal sampler outputs 20, the analog signal 18 crosses the threshold between samplers 26 and 28. When samplers are horizontally perfectly timed, the observed output is always a set of 1s at the bottom and a set of 0s at the top.
In FIG. 6, the measured sampler value at sampler 24 is a 1. At sampler 26, since the measured value 16 is offset “earlier” in time with respect to the ideal value 12, the threshold output is 0, even though it should ideally have been 1. At sampler 28, since the measured value 16 is offset “later” in time with respect to the ideal value 12, the threshold output is 1, even though it should ideally have been 0. At the subsequent samplers in FIG. 6, the ideal and real outputs are the same.
As illustrated in FIG. 6, sampler outputs with aperture and timing errors can produce an error called a bubble code or a sparkle code, which is a 0 observed in between two 1 s at the output. In such cases, there is some confusion based on the output.
After the occurrence of bubbles has been identified, there are some known approaches regarding what to do about the bubble. In one approach, the two comparators are identified between which the analog signal falls, such as observing when the comparator goes from a 1 to 0. However, in the example of FIGS. 5 and 6, since the transition from a 1 to 0 is a gentle one, such an approach would result in an incorrect or erroneous determination. Also, if there is more than one transition from 1s to 0s, a decision must be made as to which transition is the “proper” transition.
Another approach is to add up the number of 1s, which then provides an identification of the comparator above which the analog signal above was observed to make the transition. However, even in this case, this is just an estimate.
In these known approaches, bubbles are dealt with by making a choice; but, at any time, the choices will sometimes be right and sometimes be wrong.
It is desirable to provide an alternative approach to correcting aperture center errors, which reduces or eliminates the occurrences of bubbles.